Design and Implementation of a Generalized N-Digit Binary-To-Decimal Converter on an FPGA Seven-Segment Display Using Verilog Hdl

It is often needed to have circuits that can display the decimal representation of a binary number and specifically in this paper on a 7-segment display. In this paper a circuit that can display the decimal equivalent of an n-bit binary number is designed and it’s behavior is described using Verilog Hardware Descriptive Language (HDL). This HDL program is then used to configure an FPGA to implement the designed circuit


INTRODUCTION
In many electronic applications outputs are in binary form especially circuits designed using Hardware Descriptive Languages.Most of these applications require displaying the decimal equivalent of their outputs on for example a seven segment display.The design of a system that can be an interface between those outputs and a seven segment display is necessary, which is the aim of this work.

Related Work
Altera is a corporation that supplies programmable semiconductors, it provides a software tool called Quartus II to reconfigure these programmable devices.[Altera laboratory exercise, 2006] gives a basic idea of how to display the decimal equivalent of a 4-bit binary number on a seven segment display, its details are given in appendix A at the end of this paper.In addition [Wan-Fu H., 2011] has implemented a digital clock being displayed on a seven segment display, it differs with this paper in the objective but has some relevance about being both displayed on a seven segment display.

The Aim Of This Work
The aim of this work is to design a system that can display the decimal equivalent of any n-bit binary number on a seven segment display.This system is designed using Verilog HDL and then is implemented on an FPGA.In this work the idea in [Altera laboratory exercise, 2006] is developed to convert an n-bit binary number to its decimal equivalent.The complete system of this converter is explained in block form shown in Fig. 1 and then each block is designed.Each block is explained by a truth table and a program code written in verilog HDL that describes its operation.The complete system is then written in verilog HDL and then downloaded on the programmable device (the FPGA) to implement it.This paper is organized as follows, section 2 shows the block diagram of the system, and then each block in Fig. 1 is explained in detail with its code written in verilog HDL.In section 3 the systems behavior is shown including its code in Verilog HDL.
In section 4 hardware implementation and results are given.The paper is concluded in section 5.

THE PROPOSED SYSTEM BLOCK DIAGRAM
The complete design is shown in block form in Fig. 1.The block diagram is composed mainly of three circuits : 1.A circuit that compares between two numbers and produces an output accordingly, this circuit is called in this paper the compare circuit.It can be seen in Fig. 1 that there is compare(1), compare(2),….,compare(N)this will be explained in the next sections.2. A circuit that converts it's input to a value that is always between (0-9), and hence controls the seven segment display, this circuit is called in this paper the convert circuit.Since N-digits are assumed (N-seven segment displays) so there will be N-convert circuits.3. The third circuit takes the output of the convert circuit and converts it to another code that will give the right display of the decimal digit on the seven segment display, this circuit is called in this paper the seg7_display circuit.
A general idea for the block diagram in Fig. 1 is that the n-bit binary input (in the bottom left) enters the compare1 circuit.The compare1 circuit gives an output that together with the n-bit binary input enter the convert1 circuit.The output of the convert1 circuit then enters the seg7_display1 circuit.Now the latter controls the first seven segment display (HEX0) to give the required digit.The output of the compare1 circuit enters the compare2 circuit and gives an output that together with the input to the compare2 circuit enter the

Journal of Engineering Volume 19 march 2013 Number 3
333 convert2 circuit.The output of the convert2 circuit enter the seg7_display2 circuit and controls the second seven segment display (HEX1).This operation will be repeated for all digits until the full decimal number is obtained.In the next sections the operation of each circuit is explained in detail.

The Compare Circuit
The compare circuit has 1 input and 1 output as shown in Fig. 1.It checks whether its input is between [0,9] * if not then it checks if it's between [10,19] if not then it checks if it's between [20,29] and so on, and gives a unique output for each case.Table 1 shows the truth table of this circuit where its input has n bits and its output has (n-3) bits.For example If a 5-bit input is applied to the compare circuit (as in Table 1) then the output has 2 bits.As n increases the number of output bits also increases, for example if n = 6 then the decimal output is between [0,63].In this case the compare circuits output has three bits to show the seven different cases ( [0-9], [10-19], [20-29],….., [60][61][62][63]).The verilog HDL code describing the compare circuit is shown in Program code(1).

The Convert Circuit
The convert circuit has two inputs and one output, one of the inputs is the n-bit binary number and the other is the output of the compare circuit.Table 2 shows the truth table for this circuit also for a 5-bit input as in the compare circuit.Program code(2) shows the code describing the convert circuits behavior written in verilog HDL language.The convert circuit converts the input to a value that is always between 0 and 9, that will be displayed on the seven segment via the seg7_display circuit.
In Table 2 if the n-bit input (x) is 00000, 01010, 10100, or 11110 the output (Y) for all of these * The [ ] means a closed interval.
inputs is 00000, the decimal value of this output (y) is 0 which equals the first digit D 0 (first seven segment display).The second digit D 1 for the same mentioned inputs also from Table 2 equals the decimal value of the second input (z) that is the output of the compare circuit, so in order to display D 1 then z is applied to another compare circuit (compare2) and its output will be applied to another convert circuit (convert2) that will display D 1 on the seven segment display (HEX1) via the second seg7_display circuit (seg7_display2).The input z can be thought of as a control variable, let init = 10 (decimal), it can be seen from Table 2 that if z=00 then y = x-0*init, else if z =01 then y = x-init*1, else if z = 10 then y = x-init*2 , else if z = 11 then y = x-init*3, this is designed using verilog language by a while loop and making z the control variable as shown in Program code(2).

Seg7_display
The seg7_display has one n-bit input and a one 7-bit output.The input to this circuit is the output of the convert circuit which when applied to the seg7_display circuit will be decoded to another code.The seg7_display is designed in verilog HDL by [Ciletti. M. D., 2005] and the same design is used in this paper.The seven segment display shown in Fig. 1 (HEXi, where i = 0, 1, 2, …,N-1) has 7 light-emitting diodes which illuminate when a low voltage is applied to them.So by illuminating the right diodes the required decimal value is displayed.In Program code(3) the code in verilog HDL is given [Ciletti. M. D., 2005].reg [no_bit1-1:0] y; integer q; always @ (x , z) begin q = 0; while (q < (2**comt1_sig)) begin // ** means to the power if (z == q) begin y <= x -q*init; end q = q + 1; end end endmodule

THE PROPOSED SYSTEM HDL DESIGN
The complete design in verilog HDL for the block diagram of Fig. 1 is shown in Program code(4).This code shows four 7-segment displays (HEX0, HEX1, HEX2, HEX3), one for each decimal digit (it can easily be generalized to N digits).
To understand the binary-to-decimal converter circuit, take n=5.Observe Fig. 1, Table 1 and Table 2 it can be seen that: 1.If a binary input with n= 5, is applied to compare1, output ( c ) is as in Table 1. 2. Now this same binary input is applied together with ( c ) to the convert1 circuit, which gives (y) as in Table 2. Output y is always between (0-9) so if for example: The binary input is 15 (01111), the first digit is 5 and the second is 1.In this case c =01, which means that the binary input is between [10][11][12][13][14][15][16][17][18][19].
At the same time y = binary input -10, y = 15-10=5.Y is applied to the seg7_display1 that gives an output of (0010010) to the first 7segment display (HEX0).This bit pattern illuminates LED0, LED2, LED3, LED5, and LED6 of the (HEX0) 7-segment display which in return displays a 5. 3. Now to display the second digit on the second seven segment display HEX1, observe the output (z) in Table 1 it can be seen that it corresponds to the second digit.So (z) is applied to compare2 and an output z' is obtained.z together with z' is applied to convert2 and gives an output y'.y' is applied to the seg7_display2 which gives the binary bit pattern that illuminates the correct LEDs that shows the decimal value (in this example it shows a 1). 4. The same is repeated as is shown in the block diagram of Fig. 1 to display all digits on all displays.

HARDWARE IMPLEMENTATION AND RESULTS
The convert_b_to_d (program code(4)) is written in verilog HDL using Quartus II software tool version 7.2 [Altera software installation manual, 2011].Program code(4) is downloaded on an FPGA (Cyclone II EP2C20F484C7) [Cyclone II, User Guide], and the flow summary of the compilation report is shown in Table 3 and Table  4 (this flow summary is if the number of input binary bits is 10, which is the maximum number for this FPGA kit).Table 3 and 4 show that only 206 logic elements (1%) are used, which means that a very small part of the FPGA kit is reconfigured to implement this system.
In Fig. 2 the cyclone II EP2C20F484C7 starter development board is shown with the seven segment display and the toggle switches (SW) [Cyclone II, Reference manual].In the figure the toggle switches (SW (SW 0 , SW 1 , ….SW 9 )) represent the binary input and the seven segment display represent their decimal equivalent.When the toggle switches position is down (up) * then the input is logic "0" ("1").
Program code(4) The convert_b_to_d system code in Verilog HDL

CONCLUSION
In this paper a binary-to-decimal converter is designed and implemented on an FPGA.This design can be used for any number of input binary bits, which can be made directly by changing only the number of input bits in the code and increasing the number of digits that will display the decimal number.Table 3, and 4 show small part of the FPGA is reconfigured to implement this system, and since this system is used mainly as an interface between any electronic circuit implemented on an FPGA and a seven segment display then the small size is a good feature.

LIST OF ABBREVIATIONS:
FPGA: Field Programmable Gate Array.HDL: Hardware Descriptive Language.LED: Light Emitting Diode.

APPENDIX A
You are to design a circuit that converts a four-bit binary number V = v3v2v1v0 into its two-digit decimal equivalent D = d1d0.Table A1 shows the required output values.A partial design of this circuit is given in Fig. A1.It includes a comparator that checks when the value of V is greater than 9, and uses the output of this comparator in the control of the 7-segment displays.You are to complete the design of this circuit by creating a Verilog module which includes the comparator, multiplexers, and circuit A (do not include circuit B or the 7-segment decoder at this point).Your Verilog module should have the four-bit input V , the four-bit output M and the output z.

FigFig. 2
Fig. A1 Partial design of the binary-to-decimal conversion circuit.