Design and Implementation of a Generalized N-Digit Binary-To-Decimal Converter on an FPGA Seven-Segment Display Using Verilog Hdl
Main Article Content
Abstract
It is often needed to have circuits that can display the decimal representation of a binary number and specifically in this paper on a 7-segment display. In this paper a circuit that can display the decimal equivalent of an n-bit binary number is designed and it’s behavior is described using Verilog Hardware Descriptive Language (HDL).
This HDL program is then used to configure an FPGA to implement the designed circuit.
Article Details
How to Cite
Publication Dates
References
Altera corporation, Laboratory Exercise 2” Numbers and Displays” 2006, ftp://ftp.altera.com/up/pub/Laboratory_Exercises/D E1/Digital_Logic/Verilog/lab2_Verilog.pdf.
Altera Software Installation and Licensing Manual, 101 Innovation Drive, San Jose, CA 95134, November 2011 Altera Corporation.
Ciletti. M. D. , “Advanced Digital Design with the Verilog HDL”, Prentice-Hall of India, New Delhi, 2005.
Cyclone II FPGA Starter Development Board, Reference manual, Altera San Jose, CA 95134, October 2006.
Cyclone II FPGA Starter Development Kit, User Guide, Altera San Jose, CA 95134, October 2006.
Wan-Fu H., “The design of a 6-digit digital clock with a four-digit seven-segment display module”, IEEE Electrical and Control Engineering, International conference Page(s): 2656 – 2659, 2011.